// generated by chdl_uprev Tue Nov 11 16:03:05 1997

`timescale 1ns/100ps

module resistor (a, b);
    parameter    size = 1;
    input [size-1:0] a;
    output [size-1:0] b;


    RES  inst1[size-1:0] (.A(a),
                               .B(b) );
endmodule
