`timescale 1ns/1ns

module p5v (power );
// generated by Concept HDL Direct Version 13.60-s006 22-Mar-2000
// on Tue Jun 13 16:17:18 2000
// from misc/P5V/sch_1


  inout  power;
  // global signal glbl.p5v;



  `ifdef VAN

  wire  p5v;
  wire  page1_p5v;
  wire  page1_power;

  assign p5v = glbl.p5v;
  assign page1_p5v = p5v;
  assign page1_power = power;

  `endif


  `ifdef VAN

  assign power  = glbl.p5v;

  `else
  alias_bit alias_inst1 (power, glbl.p5v);

  `endif

// begin instances 

endmodule // p5v(sch_1) 
